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[VHDL-FPGA-Verilogwatch

Description: vhdl语言编写的一个秒表源码,包括在LCD上显示的部分,附带TB源码,对初学者比较实用-VHDL language, a stopwatch source, including the LCD display part, incidental TB source, more practical for beginners
Platform: | Size: 98304 | Author: ronniy | Hits:

[VHDL-FPGA-Verilogstopwatch

Description: VHDL语言设计的秒表,实现计时功能,实现报时功能,并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
Platform: | Size: 1647616 | Author: 王蕊 | Hits:

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